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82566 Gigabit Platform LAN Connect
Networking Silicon
Datasheet
Product Features

IEEE 802.3ab compliant -- Robust operation over the installed base of Category-5 (Cat-5) twisted pair cabling Robust end to end connections over various cable lengths Full duplex at 10, 100, or 1000 Mbps and half duplex at 10 or 100 Mbps. IEEE 802.3ab Auto-negotiation with Next Page support -- Automatic link configuration including speed, duplex, and flow control 10/100 downshift -- Automatic link speed adjustment with poor quality cable Automatic MDI crossover -- Helps to correct for infrastructure issues Advanced Cable Diagnostics -- Improved end-user troubleshooting Footprint compatible with 82562V devices for a single-board dual design (Gigabit and 10/100) LCI interface for a very low power 10/100 link

Gigabit LAN Connect Interface -- Low pin count, high speed interface with special low power idle modes -- Allows PHY placement proximity to I/O back panel. 3 LED outputs -- Link and Activity indications (10, 100, and 1000 Mbps) Clock supplied to MAC -- Cost optimized design Full chip power down -- Support for lowest power state 81-pin, 1.0 mm pitch, 10 mm x 10 mm FCMMAP (BGA) Package -- Smaller footprint and lower power dissipation compared to multi-chip MAC and PHY solutions. Footprint compatible with the Intel(R) 82562V Platform LAN Connect device Integrated voltage regulator and power supply control, which can be powered from a single 3.3V DC rail Operating temperatures: 0 C to 70 C and 0 C to 55 C (with internal regulator) - heat sink or forced airflow not required -- Simple Thermal Design Power Consumption less than 1.16 Watts (silicon power)
317436-003 Revision 2.4
Revision History
Date December 2007 Revision 2.4 * * August 2007 May 2007 2.3 2.2 * * * * * August 2006 2.1 * * Comments Removed 802.3 SerDes reference in section 1.0. Updated Section 1.2. Added reference document "Implementing the Intel(R) Auto Connect Battery Saver (ACBS) With the Intel(R) 82566". Added ICH9 information. Added new power consumption table for the 82566 DC/DM. Change ballout row "I" to "J". Changed all "I" pinout designations to "J". Updated crystal specifications. Replaced Figure 4. Removed Vcase parameter from Table 9. Removed section 3.4 "Thermal Diode (TD)". This information can now be found in the 82566 Gigabit Platform LAN Connect Thermal Design Considerations Application Note. Revised section 4.2 title. Revised Table 10 (removed operating temperature range parameter and related notes). Changed all "J" pinout designations to "I" to match Figure 10 "Visual Pin Assignments". Added note to Table 16.
* * * June 2006 March 2006 2.0 1.5
Initial public release. * Initial Intel Confidential release.
Legal Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel product(s) described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708296-9333. Intel(R) is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. Copyright (c) 2007, Intel Corporation. * Third-party brands and names are the property of their respective owners.
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
Contents
1.0 Introduction......................................................................................................................... 1 1.1 1.2 1.3 2.0 2.1 2.2 2.3 2.4 2.5 Document Scope................................................................................................... 2 Reference Documents...........................................................................................2 Product Codes....................................................................................................... 2 Signal Type Definitions.......................................................................................... 3 Gigabit LAN Connect Interface (GLCI) Pins.......................................................... 3 LAN Connect Interface (LCI) Pins ......................................................................... 4 Miscellaneous Pins................................................................................................ 4 PHY Pins ............................................................................................................... 5 2.5.1 LEDs......................................................................................................... 5 2.5.2 Analog Pins .............................................................................................. 5 2.5.3 Testability Pins ......................................................................................... 6 Power Supply Pins ................................................................................................ 6 Absolute Maximum Ratings................................................................................... 9 Recommended Operating Conditions ................................................................... 9 DC and AC Characteristics .................................................................................10 LED/TEST/JTAG I/F DC Specifications ..............................................................10 Power Supply Connections .................................................................................11 3.5.1 External Voltage Regulator (EVR) Power Delivery ................................11 3.5.2 Internal Voltage Regulator (IVR) Power Delivery ...................................13 3.5.3 Crystal ....................................................................................................17 Power Consumption ............................................................................................19 Package Information ...........................................................................................21 Thermal ...............................................................................................................24 Internal Pull-Up Resistors....................................................................................24 Pull-Up and Pull-Down Current ...........................................................................25 Visual Pin Assignments.......................................................................................26
Signal Descriptions............................................................................................................. 3
2.6 3.0 3.1 3.2 3.3 3.4 3.5
Voltage, Temperature, and Timing Specifications.............................................................. 9
3.6 4.0 4.1 4.2 4.3 4.4 4.5
Package and Pinout Information ......................................................................................21
Figures
1 2 3 4 5 6 7 8 9 10 82566 Block Diagram ............................................................................................ 1 External LVR Power-up Sequence......................................................................13 Internal LVR Power-up Sequence.......................................................................14 Crystal Connectivity to the 82566........................................................................18 Mechanical Drawing (1 of 4)................................................................................21 Mechanical Drawing (2 of 4)................................................................................22 Mechanical Drawing (3 of 4)................................................................................23 Mechanical Drawing (4 of 4)................................................................................24 Vpad versus Ipad ................................................................................................25 82566 Pinout (Top View - Balls Down)................................................................26
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Product Ordering Codes ....................................................................................... 2 GLCI Pins.............................................................................................................. 3 LCI Pins................................................................................................................. 4 Miscellaneous Pins ............................................................................................... 4 LED Pins ............................................................................................................... 5 Analog Pins ........................................................................................................... 5 Testability Pins ...................................................................................................... 6 Power Supply Pins ................................................................................................ 6 Absolute Maximum Ratings ................................................................................. 9 Recommended Operating Conditions ................................................................... 9 Preliminary DC and AC Characteristics .............................................................. 10 Preliminary LED/TEST/JTAG I/F DC Specifications ........................................... 10 3.3V DC External Power Supply Parameters...................................................... 11 1.8V DC External Power Supply Parameters...................................................... 11 1.0V DC External Power Supply Parameters...................................................... 12 3.3V DC External Power Supply Parameters..................................................... 13 1.8V DC Internal LVR Specification .................................................................... 15 1.0V DC Internal LVR Specification .................................................................... 15 PNP Specification for 1.8V DC LVR.................................................................... 16 PNP Specification for 1.0V DC LVR.................................................................... 17 Crystal Specifications.......................................................................................... 17 Power Consumption (82566MC/MM) .................................................................. 19 Power Consumption (82566DC/DM)................................................................... 20 Internal Pull-Up Resistors ................................................................................... 24
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
1.0
Introduction
The 82566 is a single port Gigabit Ethernet Physical Layer Transceiver (PHY) that connects to its MAC through a dedicated interconnect. The 82566 is based on Intel's Gigabit PHY technology, and supports operation at data rates of 10/100/1000 Mbps. The physical layer circuitry provides a standard IEEE 802.3 Ethernet interface for 10BASE-T, 100BASE-TX, and 1000BASE-T applications (802.3, 802.3u, and 802.3ab). This device operates with the ICH8/ICH9 chipset that incorporates and integrates the media access controller (MAC), which is referred to as the ICH8/ICH9 LAN. The 82566 is packaged in a small footprint flip chip molded matrix array package (FCMMAP) with 81 balls in a 9 x 9 array. The package size is 10 mm x 10 mm with a pitch of 1.0 mm, making it attractive for small form-factor platforms. The device interfaces with its MAC through two interfaces: Gigabit LAN Connect Interface (GLCI) and LAN Connect Interface (LCI). The GLCI is a high speed proprietary serial interface. The LCI is a low speed proprietary parallel bus. The 82566 operates using both interfaces; the GLCI for 1000 Mbps traffic and LCI for all other traffic types. Figure 1 identifies the major components of the 82566 architecture.
Figure 1. 82566 Block Diagram
LCI
GLCI
LCI
GLCI
Crystal
PLL
Multiplexer
LEDs
Testability
MDIO Status & Control
Power
Power Supply
PHY
82566
MDI
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
1.1
Document Scope
This document contains datasheet specifications for the 82566 Gigabit Platform LAN Connect (PLC), including signal descriptions, DC and AC parameters, packaging data, and pinout information.
1.2
Reference Documents
This document assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide application information:
* IEEE Standard 802.3, 2002 Edition. Incorporates various IEEE Standards previously
published separately. Institute of Electrical and Electronic Engineers (IEEE).
* IEEE Standard 1149.1, 2001 Edition (JTAG). Institute of Electrical and Electronics Engineers
(IEEE).
* * * * * *
I/O Control Hub 8 NVM Map and Programming Information. Intel Corporation. I/O Control Hub 9 NVM Map and Programming Information. Intel Corporation. Intel(R) I/O Controller Hub 8 (ICH8) Family Datasheet, Intel Corporation. Intel(R) I/O Controller Hub 9 (ICH9) Family Datasheet, Intel Corporation. Intel 965 Express Chipset Family Platform Design Guide, Intel Corporation. Intel(R) Centrino(R) Pro Processor Technology and Intel(R) Centrino(R) Duo Processor Technology Design Guide. For Intel(R) CoreTM2 Duo Processor, Mobile Intel(R) 965 Express Chipset Family and Intel(R) 82801HBM ICH8M & Intel(R) 82801HEM ICH8M-E I/O Controller Hub Based Systems, Intel Corporation. Manual. Intel Corporation.
* ICH8/ICH9 (MAC) GbE LAN Controller and 82566/82562V (PHY) Software Developer's * Implementing the Intel(R) Auto Connect Battery Saver (ACBS) With the Intel(R) 82566. Intel
Corporation.
1.3
Product Codes
Table 1 lists the product ordering codes for the 82566 device.
Table 1.
Product Ordering Codesa
Part Number RU82566DM RU82566DC RU82566MM RU82566MC Product Name Intel(R) 82566 Gigabit Platform LAN Connect Device Intel(R) 82566 Gigabit Platform LAN Connect Device Intel(R) 82566 Gigabit Platform LAN Connect Device Intel(R) 82566 Gigabit Platform LAN Connect Device Description Business Desktop GbE LAN connection Consumer Desktop GbE LAN connection Business Mobile GbE LAN connection. Consumer Mobile GbE LAN connection
a. For more information regarding the differences, please contact your Intel field representative.
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
2.0
2.1
Signal Descriptions
Signal Type Definitions
The signals are defined as follows in the table below:
Type In (I) Out (O) T/S S/T/S O/D A-in A-out P B PU PD Standard input-only signal. Standard output-only signal. Bi-directional, tri-state input/output signal. Sustained tri-state signal. Open drain signal. Analog input signal. Analog output signal. Power signal. Input bias. Pull-up. Pull-down. Description
2.2
Table 2.
Gigabit LAN Connect Interface (GLCI) Pins
GLCI Pins
Signal Name GLAN_RXP GLAN_RXN GLAN_TXN GLAN_TXP KBIAS_P KBIAS_N Ball J4 H4 J2 H2 G7 H7 Type A-in A-out B Description GLCI Serial Data Input. This is the differential input for GLCI (MAC to PHY). GLCI Serial Data Output. This is the differential output for GLCI (MAC to PHY). Impedance Compensation. External 1.4 K 1% resistors should be used.
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
2.3
Table 3.
LAN Connect Interface (LCI) Pins
LCI Pins
Signal Name Ball Type Description LCI/GLCI Clock. The clock is driven by the 82566 according to the operation mode: * JKCLK E2 O * * * In 1000 Mbps mode, JKCLK frequency is 62.5 MHz. In 100 Mbps mode, JKCLK frequency is 50 MHz. In 10 Mbps mode, JKCLK frequency is 5 MHz. In power down mode, JKCLK frequency is 0 MHz.
Reset/SYNC. This pin is driven by the MAC and has two functions: * JRSTSYNC E3 I * Reset. When this pin is asserted beyond one LCI clock, the 82566 refers to this signal as a reset signal. However, to ensure that the 82566 resets, the reset should remain active for at least 500 s. This functionality is also used to bring the 82566 out of a power-down state. SYNC. When this pin is activated synchronously for one LCI clock only, it is used for synchronization between the MAC and the 82566 on LCI word boundaries.
JTXD2 JTXD1 JTXD0 JRXD2 JRXD1 JRXD0
F1 F3 D1 C1 D2 D3 O I
LCI Transmit Data. These pins are used for receiving real time control and management data transmitted by the ICH8/ICH9 LAN. These pins are also used to move out of band control from the MAC to the 82566. The pins should be fully synchronous to JKCLK. LCI Receive Data. These pins are used for transmitting real time control and management data received by the ICH8/ICH9 LAN. These pins are also used to move out of band control from the 82566 to the MAC.
2.4
Table 4.
Miscellaneous Pins
Miscellaneous Pins
Signal Name THERM_D_P THERM_D_N Ball A2 A3 J6 J7 RESERVED A6 B5 C5 N/A No Connect. These pins must not be connected to any external circuitry. Pull-up or pull-down resistors should not be connected to these pins. Type A-out Description Thermal Diode Reference. This pin can be used to measure the silicon temperature within the device.
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
2.5
2.5.1
Table 5.
PHY Pins
LEDs
LED Pinsa
Signal Name LED0 LED1 LED2 Ball A4 B4 A5 Type O O O Description LED0. This signal is used for the programmable LED. It is programmed through the Intel(R) ICH8/ICH9 NVM word 18h. LED1. This signal is used for the programmable LED. It is programmed through the Intel(R) ICH8/ICH9 NVM word 17h. LED2. This signal is used for the programmable LED. It is programmed through the Intel(R) ICH8/ICH9 NVM word 18h.
a. The I/O Control Hub 8 /ICH9 NVM Map and Programming Information Application Notes can be referenced for details regarding the programming of the LEDs and the various modes.
2.5.2
Table 6.
Analog Pins
Analog Pins
Signal Name MDI_PLUS[0] MDI_MINUS[0] MDI_PLUS[1] MDI_MINUS[1] MDI_PLUS[2] MDI_MINUS[2] MDI_PLUS[3] MDI_MINUS[3] IEEE_TEST_P IEEE_TEST_N RBIAS_P RBIAS_N XTAL1 XTAL2 Ball B8 B9 D9 D8 F9 F8 H8 H9 A7 B7 E7 E6 H6 H5 A-out A Type A Description Media Dependent Interface [0]. In MDI configuration, MDI_PLUS[0]+/- is used for the transmit pair and in MDI-X configuration MDI_MINUS[0]+/- is used for the receive pair. Media Dependent Interface [1]. In MDI configuration, MDI_PLUS[1]+/- is used for the receive pair and in MDI-X configuration MDI_MINUS[1]+/- is used for the transmit pair. Media Dependent Interface [2:3]. For 1000BASE-T MDI configuration, MDI_PLUS[2:3]+/- is used for the receive pair and in MDI-X configuration MDI_MINUS[2:3]+/- is used for the transmit pair. These pins are not used for 100BASE-TX and 10BASE-T. Analog Test Pins Output. These are used for measurement of the transmitter 125 MHz clock jitter. Compensation Reference Resistor. A 1.4 K, 1% tolerance resistor should be used. RBIAS_N should also be connected to ground (VSS). Crystal In. These pins can be driven by an external 25 MHz crystal or by an external MOS level 25 MHz oscillator. It is also used as the clock reference for the PHY.
A
B A-in A-out
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
2.5.3
Table 7.
Testability Pins
Testability Pins
Signal Name JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS TEST_EN Ball G1 H1 G3 G2 B6 Type I I/PU T/S I/PU I JTAG Clock Input JTAG TDI Input JTAG TDO Output JTAG TMS Input Test Mode Enable. This signal enables test mode capabilities. It should be strapped to GND for normal operation. Description
2.6
Table 8.
Power Supply Pins
Power Supply Pins (Sheet 1 of 2)
Signal Name VCC3P3 VCC3P3 VCC1P8 VCC1P8 VCC1P8 VCC1P8 CTRL_18 VCC VCC1P0 VDD1P0 VDD1P0 VCCF1P0, VCCFC1P0 CTRL_10 Ball F2 B3 C2 G5 F5 D5 B2 D4 E4 G4 F7 D7 E8 E5 H3 C3 P Out 1.0V DC Normal Operation. 1.0V Control. This is the voltage control signal for the external PNP transistor that generates the 1.0V supply. P 1.0V DC Supply. This is connected to the PHY. Out P P 1.8V Control. This is the voltage control signal for the external PNP transistor that generates the 1.8V supply. 1.0V DC Supply. This is connected to the 82566 core. 1.0V DC Supply. This is connected to the GLCI circuits. P 1.8V DC Supply. This is connected to the 82566. Type P Description 3.3V DC Supply. This is connected to the 82566.
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
Table 8.
Power Supply Pins (Sheet 2 of 2)
Signal Name Ball Type Description 1.0V DC Output. This output is from the on-die internal regulator. This signal should be connected to VCC1P8 when external voltage regulators are used or in IVRd mode. V1P0_OUT should be connected to VCC1P0 for IVRi mode.
V1P0_OUT
B1
P
A1
VSS
C4 E1 F4 A8 A9 C6 C7 C8 C9 D6 E9
P
Ground
VSSA
F6 G6 G8 G9 J1 J3 J5 J8 J9
P
Analog Ground
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
3.0
3.1
Table 9.
Voltage, Temperature, and Timing Specifications
Absolute Maximum Ratings
Absolute Maximum Ratingsa
Symbol Tstorage Vi Vo VCCP VCC1p8 VCC1p0 Parameterb Storage Temperature Range 3.3V DC Digital Compatible I/O Voltage Analog 1.0V DC I/O Voltage Analog 1.8V DC I/O Voltage 3.3V Periphery Voltage Range 1.8V Analog Voltage Range 1.0V DC Core/Analog DC Supply Voltage Minc -65 -0.5 -0.2 -0.3 -0.5 -0.3 -0.2 Max 140 4.6 1.68 2.52 4.6 2.52 1.68 V V V V Unit C
a. Ratings in this table are those beyond which permanent device damage is likely to occur. These values should not be used as the limits for normal device operation. Exposure to these absolute maximum rating conditions for extended periods may affect device reliability. b. Recommended operating conditions require the accuracy of a power supply of +/- 5% relative to the nominal voltage. c. Maximum ratings are referenced to ground (VSS).
3.2
Recommended Operating Conditions
Table 10. Recommended Operating Conditions
Symbol VCCP VCC1p8 VCC1p0 Parameter Periphery Voltage Range Core Digital Voltage Range Core/Analog Voltage Range Min 3.0 1.71 0.95 Max 3.6 1.89 1.05 Unit V V V
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
3.3
DC and AC Characteristics
Table 11. Preliminary DC and AC Characteristics
Symbol VIL VIH VOL VOH Vhys Iil IOFF PU Cin Cout Parameter Voltage input LOW Voltage input HIGH Voltage output LOW Voltage output HIGH Hysteresis Input Current Current at IDDQ Mode Internal Pull-Up Input capacitance Load capacitance @ 160 MHz VCC-Max; VI=3.6V DC/GND Condition IOL= -12 mA; VCC=Min IOL=-100 A; VCC=Min IOH= -16 mA; VCC=Min IOH=-100 A; VCC=Min Min 2.0 2.4 VCC-0.2 160 2.7 Max 0.8 0.4 0.2 15 50 8.6 2.5 16 Unit V V V V mV A A K pF pF
b c d d
Notes a
a. The input buffer has a hysteresis greater than 160 mV. b. IDDQ mode maximum current consumption: CORE_VCCP: 15 A; VCCP: 35 A c. The internal pull-up maximum was characterized at slow corner (110C, VCC=min, process slow); and the internal pull-up minimum, at fast corner (0C, VCC=max, process fast). d. Pad Cin = 2.5 pF (maximum input capacitance), and Cout = 16 pF (characterized maximum output load capacitance per 160 MHz).
3.4
LED/TEST/JTAG I/F DC Specifications
Table 12. Preliminary LED/TEST/JTAG I/F DC Specifications
Symbol VCCP Vih Vil Vleak Voh Vol Cin Parameter Periphery Supply Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance Condition 0 < Vin< VCCP Iout = -16 mA Iout = -0.1 mA Iout = -12 mA Min 3.0 2.0 -0.3 2.4 Max 3.6 VCC +0.3 0.8 20 0.2 0.4 2.5 Unit V V V A V V pF Notes
-
-
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
3.5
Power Supply Connections
There are two options in providing power to the 82566:
* Connecting the 82566 to three external power supplies with nominal voltages of 3.3V DC,
1.8V DC, and 1.0V DC, which is covered in Section 3.5.1.
* Powering the 82566 with only an external 3.3V DC supply and using internal power regulators
from the device itself combined with external PNP transistors to supply the 1.8V DC and 1.0V DC levels as described in Section 3.5.2.
3.5.1
External Voltage Regulator (EVR) Power Delivery
The following power supply requirements apply to designs where the 82566 is supplied by external voltage regulators (EVRs). These systems do not use the internal regulator logic built into the device as described in Section 3.5.2.
Table 13. 3.3V DC External Power Supply Parameters
Title Rise Time Monotonicity Description Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any given time between 10% and 90% Slope Min: 0.8*V(min)/Rise time (max) Max: 0.8*V(max)/Rise time (min) Operational Range Ripple Overshoot Voltage range for normal operating conditions Maximum voltage ripple (peak to peak)a Maximum overshoot allowed 3.0 3.6 100 100 V mV mV 24 28800 V/s Min 0.1 Max 100 0 Units ms mV
a. This is dependent on capacitance.
Table 14. 1.8V DC External Power Supply Parameters
Title Rise Time Monotonicity Description Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any given time between 10% and 90% Slope Min: 0.8*V(min)/Rise time (max) Max: 0.8*V(max)/Rise time (min) Operational Range Ripple Voltage range for normal operating conditions Maximum voltage ripple (peak to peak)a 1.71 1.89 40 V mV 14 V/s Min 0.1 Max 100 0 Units ms mV
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
Table 14. 1.8V DC External Power Supply Parameters
Title Overshoot Decoupling Capacitance Capacitance ESR Description Maximum overshoot allowed Capacitance range Equivalent series resistance of output capacitance Min 15 Max 100 25 50 Units mV F m
a. This is dependent on capacitance.
Table 15. 1.0V DC External Power Supply Parameters
Title Rise Time Monotonicity Description Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any given time between 10% and 90% Slope Min: 0.8*V(min)/Rise time (max) Max: 0.8*V(max)/Rise time (min) Operational Range Ripple Overshoot Decoupling Capacitance Capacitance ESR Voltage range for normal operating conditions Maximum voltage ripple (peak to peak)b Maximum overshoot allowed Capacitance range Equivalent series resistance of output capacitance 0.95 15 1.05a 40 100 25 50 V mV mV F m 7.6 17 V/s Min 0.1 Max 100 0 Units ms mV
a. To reduce BOM costs, the ICH8/ICH9 1.05V +/-5% supply can be used. b. This is dependent on capacitance.
3.5.1.1
In-Rush Current
To meet 375 mA in-rush current requirements (not including external capacitors), the ramp time should be 5 ms to 100 ms on all power rails. For faster ramps (100 s to 5 ms), higher in-rush current is expected due to the high charging current of the decoupling capacitors on the 3.3V DC, 1.8V DC, and 1.0V DC power rails.
3.5.1.2
82566 Power Up Sequence (External LVR)
Designs must comply with power sequencing requirements to avoid latch-up and forward-biased internal diodes. The board designer controls the power up sequence with the following stipulations:
* 1.8V must not exceed 3.3V by more than 0.3 V. * 1.0V must not exceed 3.3V by more than 0.3 V.
For power down, there is no requirement (only charge that remains is stored in the decoupling capacitors).
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
Figure 2. External LVR Power-up Sequence
3.5.2
Internal Voltage Regulator (IVR) Power Delivery
The 82566 has two IVR controllers. One for the 1.8V supply and one for the 1.0V supply. There are two IVR modes of operation known as IVRd and IVRi. IVRd uses two external transistors to generate the 1.8V and 1.0V supplies. In this mode, these two voltages are stepped down from a 3.3V DC source. IVRi mode uses an external transistor to generate the 1.8V supply and an internal transistor to generate the 1.0V supply. In this mode, the 1.8V supply is stepped down from a 3.3V DC source, and the 1.0V supply is stepped down from the 1.8V DC supply.
Table 16. 3.3V DC External Power Supply Parameters
Title Rise Time Monotonicity Description Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any given time between 10% and 90% Slope Min: 0.8*V(min)/Rise time (max) Max: 0.8*V(max)/Rise time (min) Operational Range Ripple Overshoot Voltage range for normal operating conditions Maximum voltage ripple (peak to peak) @ f < 20 MHz Maximum overshoot allowed Maximum overshoot allowed duration. (At that time delta voltage should be lower than 5 mV from steady state voltage) 0.05 ms 3.0 3.6 100 100 V mV mV 24 9.5 mV/ms Min 0.1 Max 100 0 Units ms mV
Overshoot Settling Time
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
3.5.2.1
In-Rush Current
To meet 375 mA in-rush current requirements, the ramp time should be 5 ms to 100 ms on the 3.3V DC power rail. For faster ramps (100 s to 5 ms), higher in-rush current is expected due to the high charging current of the decoupling capacitors on the 3.3V DC power rail.
3.5.2.2
82566 Power Up Sequence (Internal LVR)
The 82566 controls the power up sequence internally and automatically with the following conditions:
* 3.3V must be the source for the internal LVR. * 1.8V will never exceed the 3.3V. * 1.0V will never exceed 3.3V or 1.8V.
The ramp is delayed internally, with Tdelay depending on the rising slope of the 3.3V ramp. For power down, there is no requirement (only charge that remains is stored in the decoupling capacitors). Figure 3. Internal LVR Power-up Sequence
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
3.5.2.3
1.8V DC Internal LVR Specification
Table 17. 1.8V DC Internal LVR Specification
Value Parameter Minimum Input Voltage (V_in) Input Voltage Slew Rate (V_in_rise) DC Output Voltage (Vdd1p8) 3.0 1.71 5 3 Maximum 3.6 1.89 V ms V Typically 3.3V Typically 5 ms Measured on the internal sense point. Typically 300 mA Both for 1.8V DC and 1.0V DC LVRs The peak to peak output ripple is measured at 20 MHz Bandwidth. Typically -40 dB Units Comments
Output Current (I_vdd1p8)
950
mA
Turn-On Time (T_on)
10
ms
Peak-to-Peak Output Ripple (Vac)
-
50
mV
Power Supply Rejection Ratio (1p8_PSRR) 1p8 LVR Voltage @ Over/Under Shoot Event (1p8_event)
-
-20 50
dB mV
3.5.2.4
1.0V DC Internal LVR Specification
Table 18. 1.0V DC Internal LVR Specification
Value Parameter Minimum Input Voltage (V_in) Input Voltage Slew Rate (V_in_rise) DC Output Voltage (V1p0_out) 3.0 0.95 Maximum 3.6 1.05 V ms V Typically 3.3V Typically 5 ms Measured on the internal sense point. Typically 200 mA Units Comments
Output Current (I_v1p0)
5
400
mA
15
82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
Table 18. 1.0V DC Internal LVR Specification
Value Parameter Minimum Turn-On Time (T_on) 3 Maximum 10 ms Both for 1.8V DC and 1.0V DC LVRs Both for 1.8V DC and 1.0V DC LVRs. Peak-to-Peak Output Ripple (Vac) 50 mV The peak to peak output ripple is measured at 20 MHz Bandwidth. Typically -40 dB Units Comments
Power Supply Rejection Ratio (1p0_PSRR)
-
-20
dB
3.5.2.5
PNP Transistor Specification for 1.8V DC LVR
Table 19. PNP Specification for 1.8V DC LVR
PNP Connection Description DC Gaina Transition Frequency PNP Transistor for 1.8V DC LVR, using internal Transistor for 1.0V DC LVR Thermal Resistance Junction to Ambientb Maximum Operation Junction Temperature Maximum Collector Current Maximum total power dissipationc DC Gaind Transition Frequency PNP Transistor for 1.8V DC LVR, using external Transistor for 1.0V DC LVR Thermal Resistance Junction to Ambientb Maximum Operation Junction Temperature Maximum Collector Current Maximum Power Dissipatione Symbol Min 60 60 Typ 40 40 Max 400 60 150 1 1.2 400 60 150 1 1.2 MHz C/W C A W V MHz C/W C A W Units
fT Rt_ja Tj_max Ic_max Pmax
fT Rt_ja Tj_max Ic_max Pmax
a. Vce = 0.4 V DC; Ic = 1 A; T = 25 C. b. The thermal resistance feature depends on the PNP package along with the board layout including: number of layers, layer thickness, copper area for collector pad, and component locations. c. Ta = 70 C; Vin = 3.6 V DC; Vout = 1.71 V DC; I = 0.95 A; 1.4 5% Series Resistor. d. Vce = 1 V DC; Ic = 0.5 A; T = 25 C. e. Ta = 70 C; Vin = 3.6 V DC; Vout = 1.7 1 V DC; I = 0.55 A.
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
3.5.2.6
PNP Transistor Specification for 1.0V DC LVR
Table 20. PNP Specification for 1.0V DC LVR
PNP Connection Description dc Gaina Transition Frequency Thermal Resistance Junction to Ambientb Maximum Operation Junction Temperature Maximum Collector Current Maximum Power Dissipationc Symbol Min 60 Typ 40 Max 400 60 150 1 1.1 Units MHz C/W C A W
fT Rt_ja Tj_max Ic_max Pmax
PNP Transistor for 1.0V DC LVR
a. Vce = -1.0 V DC; Ic = 0.5 A; T = 25 C. b. The thermal resistance feature depends on the PNP package along with the board layout including: number of layers, layer thickness, copper area for collector pad, and component locations. c. Ta = 70 C; Vin = 3.6 V DC; Vout = 0.95 V DC; I = 0.4 A
3.5.3
Crystal
Table 21 lists the recommended crystal specifications for operation with the 82566.
Table 21. Crystal Specifications (Sheet 1 of 2)
Parameter Name Frequency Vibration mode Cut Operating/Calibration Mode Frequency Tolerance Temperature Tolerance Operating Temperature Non Operating Temperature Equivalent Series Resistance (ESR) Load Capacitance Shunt Capacitance Pullability from Nominal Load Capacitance Max Drive Level Insulation Resistance Aging Symbol fo f/fo @25C f/fo Topr Topr Rs Cload Co f/Cload DL IR f/fo Recommended Value 25.000 MHz Fundamental AT Parallel 30 ppm 30 ppm -20 to +70 C -40 to +90 C 10 20 pF (max 24 pF) 6 pF 15 ppm/pF max 500 W 500 M min 5 ppm per year 5 ppm per year Max/Min Range a a a -
Conditions @25 C @25 C @25 MHz @ 100V DC -
50
a a
-
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
Table 21. Crystal Specifications (Sheet 2 of 2)
Parameter Name Differential Board Capacitance Board Capacitance External Capacitors Board Resistance Symbol CD Cs C1, C2 Rs Recommended Value 2 pF 4 pF 27 pF 0.1 Max/Min Range
b c a
Conditions
-
1
a. When not using values within 1% of the recommended values, the following procedures must be used: 1. On the board with the crystal and the 82566, measure the clock at the output of the receive and transmit lines. 2. Change C1 and C2 to meet with the 25 MHz requirement. 3. Ensure the demand on the 25 MHz clock has a deviation of less then 100 ppm (for example, 25 0.0025 MHz). 4. If the measured frequency is higher then 25.0025 MHz, replace capacitors C1 and C2 with larger capacitors. 5. If the measured frequency is lower then 24.9975 MHz, replace capacitors C1 and C2 with smaller capacitors. b. Differential board capacitance is the capacitance between Ser_CLK_PLUS and Ser_CLK_MINUS. c. Board capacitance is the differential capacitance between the input and output. This parasitic capacitance must be less than or equal to the specification. This value can change up to 10%. The procedures listed in footnote "a" must be followed to comply with the ppm specification.
Figure 4. Crystal Connectivity to the 82566
Crystal
Crystal Pad
"B"
Capacitor 90 mils
"B"
Capacitor
Crystal Pad
90 mils
27pF 0402
"A"
27pF 0402
Less than 660 mils
"C"
Resistor 30-ohm 0402
Xtal2
Xtal1
Ethernet Controller
Note:
Refer to Technical Advisory (TA-181), the 82566 Board Layout Checklist, and the 82566 Design Checklist for details relating to Figure 4.
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
3.6
Power Consumption
This section lists the estimated targets for the 82566 power. The numbers apply to the device current and power but do not include power losses on external components.
Table 22. Power Consumption (82566MC/MM)
System State 3.3V Current (mA) 1.8V Current (mA) 1.0V Current (mA) 82566 Device Only Power (mW) External LVR 1180 1161 1141 424 405 343 150 150 108 Solution Powera (mW)
Link State
So (Max)
1000 Mbps Active 1000 Mbps Active 1000 Mbps Idle 100 Mbps Active 100 Mbps Idle 10 Mbps Active 10 Mbps Idle Cable Disconnect (no SPD, LVR on)
28 26 25 33 27 17 15 15 17
440 441 442 145 145 148 46 46 24
297 281 263 56 56 19 18 18 10
2525 2468 2409 772 752 607 261 261 168
S0 (Typ)
Cable Disconnect (SPD, LVR on) Cable Disconnect (no Intel(R) ACBSb, LVR off, no wake) Cable Disconnect (Intel(R) ACBS, LVR off, wake)c Cable Disconnect (Intel(R) ACBS, 3.3V power disabled, wake)c 100 Mbps Idle (wake) 10 Mbps Idle (wake)
12
0
0
40
40
12
0
0
40
40
0
0
0
0
0
29 19 12 12
144 46 0 0
56 18 0 0
411 159 40 40
756 271 40 40
Sx (Typ)
No Link (no wake) PD, LVR off LAN Disable
a. Solution power is the total amount of power from the 3.3V supply required for the 82566 to operate. In its mathematical form: solution power = (82566 current) * 3.3V. The 3.3V is assumed since this is the normal voltage rail provided to the LAN solution. b. Intel(R) ACBS refers to the Intel(R) Auto-Connect Battery Saving feature. c. An additional 7 mW of power is consumed on the 3.3V rail by the external link detect circuitry while the device is in ACBS mode.
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
Table 23. Power Consumption (82566DC/DM)
System State 3.3V Current (mA) 1.8V Current (mA) 1.0V Current (mA) 82566 Device Only Power (mW) External LVR 1180 1161 1141 424 405 343 150 150 108 411 159 180 40 40 Solution Powera (mW)
Link State
So (Max) S0 (Typ)
1000 Mbps Active 1000 Mbps Active 1000 Mbps Idle 100 Mbps Active 100 Mbps Idle 10 Mbps Active 10 Mbps Idle Cable Disconnect (no SPD, LVR on) Cable Disconnect (SPD, LVR on) 100 Mbps Idle (wake) 10 Mbps Idle (wake)
28 26 25 33 27 17 15 15 17 29 19 21 12 12
440 441 442 145 145 148 46 46 24 144 46 109 0 0
297 281 263 56 56 19 18 18 10 56 18 50 0 0
2525 2468 2409 772 752 607 261 261 168 756 271 292 40 40
Sx (Typ)
No Link Idle (wake) No Link (no wake) - PD LAN Disable
a. Solution power is the total amount of power from the 3.3V supply required for the 82566 to operate. In its mathematical form: solution power = (82566 current) * 3.3V. The 3.3V is assumed since this is the normal voltage rail provided to the LAN solution.
The current from the 82566 does not change regardless of generating the 1.0V using the on-die transistor or an external pass transistor. The total current demand remains constant, but the power dissipated by the 82566 package changes. The 1.0V power is either on-die or at the external pass transistor.
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82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
4.0
Package and Pinout Information
The physical characteristics of the 82566 are described in this section. The pin number to signal mapping is indicated in Section 4.5.
4.1
Package Information
The package used for the 82566 is an 81-pin, 10 mm x 10 mm, small footprint FCMMAP (BGA) with a ball pitch of 1.0 mm.
Figure 5. Mechanical Drawing (1 of 4)
21
82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
Figure 6. Mechanical Drawing (2 of 4)
22
82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
Figure 7. Mechanical Drawing (3 of 4)
NOTES: 1). DIMENSION APPLY AFTER SOLDER BALL REFLOW. 2). INTERPRET DIMENSIONS AND TOLERANCES IN ACCORDANCE WITH ASME Y14.5M-1994. 3). DIMENSION ENCLOSED IN PARENTHESES ARE FOR REFERENCE ONLY
SEE DETAIL
A
ITEM A
DIMENSION 1.7450.07
INCOMING BALL SIZE(mm) N/A
DETAIL 1.0 mm BALL PITCH 1.0 mm BALL PITCH
B
0.5150.035
0.610
23
82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
Figure 8. Mechanical Drawing (4 of 4)
DETAIL A SCALE 50:1
4.2
Thermal
The 82566 is specified for operation when the Ambient Temperature (TA) is within the range of 0 C to 55 C. For information about the thermal characteristics of the 82566, including operation outside this range, refer to the 82566 Gigabit Platform LAN Connect Thermal Design Considerations Application Note.
4.3
Internal Pull-Up Resistors
Table 24 lists the internal pull-up resistors and their functionality in different device states. Each internal pull-up resistor has a nominal value of 5 K, ranging from 2.7 K to 8.6 K.
Table 24. Internal Pull-Up Resistors
Signal Name (Ball Location) LED0 (A4) LED1 (B4) LED2 (A5) JTAG_TCK (G1) JTAG_TDI (H1) JTAG_DO (G3) JTAG_TMS (G2) JTXD[2:0] (F1, F3, D1) JRXD[2:0] (C1, D2, D3) Default State Not connected Not connected Not connected Not connected Connected Not connected Connected Not connected Not connected Power-Down Statea Connected Connected Connected Connected Connected Connected Connected Connected Connected
a. This column describes the state of the internal pull-up resistors in device power-down mode when the internal voltage regulators are shut down.
24
82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
4.4
Pull-Up and Pull-Down Current
1. External R pull-down recommended value: 400 2. External R pull-up recommended value: 3 K 3. External buffer recommended strength: 2 mA 4. As the internal pull-up acts as a current source, the external pull-down resistor can be as low as required without raising the output current.
Figure 9. Vpad versus Ipad
Ipad[mA]
OV
50%VCCP
Vpad
5. The internal pull-up maximum was characterized at the fast corner (0C, VCCP=3.6V, process fast). 6. The internal pull-up minimum was characterized at the slow corner (115C, VCCP=2.9V, process slow).
25
82566 Gigabit Platform LAN Connect Networking Silicon Datasheet
4.5
Visual Pin Assignments
Figure 10. 82566 Pinout (Top View - Balls Down)
GLAN_ TXN GLAN_ TXP JTAG_ TMS VCC3P3
VSSA
VSSA
RSV
RSV
VSSA
GLAN_ RXP GLAN_ RXN VCC1P0
VSSA
VSSA J JTAG_TDI H JTAG_ TCK JTXD2 F
MDI_ MDI_ MINUS[3] PLUS[3] VSSA MDI_ PLUS[2] VSSA MDI_ PLUS[1] VSSA VSSA
KBIAS_N
XTAL1
XTAL2
VCCFC1P0
KBIAS_P
VSSA
VCC1P8
JTAG_ TDO JTXD1
G
MDI_ VDD1P0 MINUS[2] VDD1P0
VSSA
VCC1P8
VSS
RBIAS_P RBIAS_N VCCF1P0
VCC
JRSTSYNC
JKCLK
VSS E
MDI_ VDD1P0 MINUS[1] VSSA VSSA IEEE_ TEST_N IEEE_ TEST_P 7
VSSA
VCC1P8
VCC
JRXD0
JRXD1
JTXD0 D
VSSA
RSV
VSS
CTRL_10 VCC1P8
JRXD2 C V1P0_ OU T VSS 1
MDI_ MDI_ MINUS[0] PLUS[0] VSSA 9 VSSA 8
TEST_EN
RSV
LED1
VCC3P3 CTRL_18 THERM_ THERM_ D_N D_P 3 2
B
RSV 6
LED2 5
LED0 4
A
NOTE: Some names in the pinout in Figure 10 may differ from the signal names in order for the pinout to be more easily read.
26

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